SH7713 datasheet(312/904 Pages) RENESAS

312 / 904 page

Section 9 User Break Controller

Rev.1.50 Aug. 30, 2006 Page 272 of 860

REJ09B0288-0150

9.2.8

Break Bus Cycle Register B (BBRB)

BBRB is a 16-bit readable/writable register, which specifies (1) X bus or Y bus, (2) L bus cycle or

I bus cycle, (3) instruction fetch or data access, (4) read or write, and (5) operand size in the break

conditions of channel B.

Bit

Bit Name

Initial

Value

R/W

Description

15 to 10



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

XYE

R/W

Selects the X memory bus or Y memory bus as the

channel B break condition. Note that this bit setting is

enabled only when the L bus is selected with the CDB1

and CDB0 bits. Selection between the X memory bus

and Y memory bus is done by the XYS bit.

0: Selects L bus for the channel B break condition

1: Selects X/Y memory bus for the channel B break

condition

XYS

R/W

Selects the X bus or the Y bus as the bus of the

channel B break condition.

0: Selects the X bus for the channel B break condition

1: Selects the Y bus for the channel B break condition

CDB1

CDB0

R/W

L Bus Cycle/I Bus Cycle Select B

Select the L bus cycle or I bus cycle as the bus cycle of

the channel B break condition.

00: Condition comparison is not performed

01: The break condition is the L bus cycle

10: The break condition is the I bus cycle

11: The break condition is the L bus cycle

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