SH7713 datasheet(309/904 Pages) RENESAS

309 / 904 page

Section 9 User Break Controller

Rev.1.50 Aug. 30, 2006 Page 269 of 860

REJ09B0288-0150

9.2.4

Break Address Register B (BARB)

BARB is a 32-bit readable/writable register. BARB specifies the address used as a break condition

in channel B. Control bits CDB1, CDB0, XYE, and XYS in BBRB select one of the four address

buses for break condition B.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 0

BAB31 to

BAB 0

All 0

R/W

Break Address B

Stores an address which specifies a break condition in

channel B.

If the I bus or L bus is selected in BBRB, an IAB or LAB

address is set in BAB31 to BAB0.

If the X memory is selected in BBRB, the values in bits 15

to 1 in XAB are set in BAB31 to BAB17. In this case, the

values in BAB16 to BAB0 are arbitrary.

If the Y memory is selected in BBRB, the values in bits 15

to 1 in YAB are set in BAB15 to BAB1. In this case, the

values in BAB31 to BAB16, and BABO are arbitrary.

Table 9.1

Specifying Break Address Register

Bus Selection in

BBRB

BAB31 to BAB17

BAB16

BAB15 to BAB1

BAB0

L bus

LAB31 to LAB0

I bus

IAB31 to IAB0

X bus

XAB15 to XAB1

Don't care

Y bus

Don’t care

Don't care

YAB15 to YAB1

Don't care

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