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SH7713 Datasheet(PDF) 308 Page - Renesas Technology Corp |
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SH7713 Datasheet(HTML) 308 Page - Renesas Technology Corp |
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308 / 904 page ![]() Section 9 User Break Controller Rev.1.50 Aug. 30, 2006 Page 268 of 860 REJ09B0288-0150 Bit Bit Name Initial Value R/W Description 5 4 IDA1 IDA0 0 0 R/W R/W Instruction Fetch/Data Access Select A Select the instruction fetch cycle or data access cycle as the bus cycle of the channel A break condition. 00: Condition comparison is not performed 01: The break condition is the instruction fetch cycle 10: The break condition is the data access cycle 11: The break condition is the instruction fetch cycle or data access cycle 3 2 RWA1 RWA0 0 0 R/W R/W Read/Write Select A Select the read cycle or write cycle as the bus cycle of the channel A break condition. 00: Condition comparison is not performed 01: The break condition is the read cycle 10: The break condition is the write cycle 11: The break condition is the read cycle or write cycle 1 0 SZA1 SZA0 0 0 R/W R/W Operand Size Select A Select the operand size of the bus cycle for the channel A break condition. 00: The break condition does not include operand size 01: The break condition is byte access 10: The break condition is word access 11: The break condition is longword access |
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