SH7713 datasheet(306/904 Pages) RENESAS

Part #	SH7713

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	904 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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306 / 904 page

Section 9 User Break Controller

Rev.1.50 Aug. 30, 2006 Page 266 of 860

REJ09B0288-0150

9.2

The user break controller has the following registers. For details on register addresses and access

sizes, refer to section 23, List of Registers.

• Break address register A (BARA)

• Break address mask register A (BAMRA)

• Break bus cycle register A (BBRA)

• Break address register B (BARB)

• Break address mask register B (BAMRB)

• Break bus cycle register B (BBRB)

• Break data register B (BDRB)

• Break data mask register B (BDMRB)

• Break control register (BRCR)

• Execution times break register (BETR)

• Branch source register (BRSR)

• Branch destination register (BRDR)

• Break ASID register A (BASRA)

• Break ASID register B (BASRB)

9.2.1

Break Address Register A (BARA)

BARA is a 32-bit readable/writable register. BARA specifies the address used as a break condition

in channel A.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 0

BAA31 to

BAA 0

All 0

R/W

Break Address A

Store the address on the LAB or IAB specifying break

conditions of channel A.

SH7713 Datasheet(PDF) 306 Page - Renesas Technology Corp