SH7713 datasheet(307/904 Pages) RENESAS

307 / 904 page

Section 9 User Break Controller

Rev.1.50 Aug. 30, 2006 Page 267 of 860

REJ09B0288-0150

9.2.2

Break Address Mask Register A (BAMRA)

BAMRA is a 32-bit readable/writable register. BAMRA specifies bits masked in the break address

specified by BARA.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 0

BAMA31 to

BAMA 0

All 0

R/W

Break Address Mask A

Specify bits masked in the channel A break address

bits specified by BARA (BAA31–BAA0).

0: Break address bit BAAn of channel A is included in

the break condition

1: Break address bit BAAn of channel A is masked and

is not included in the break condition

Note:

n = 31 to 0

9.2.3

Break Bus Cycle Register A (BBRA)

BBRA is a 16-bit readable/writable register, which specifies (1) L bus cycle or I bus cycle, (2)

instruction fetch or data access, (3) read or write, and (4) operand size in the break conditions of

channel A.

Bit

Bit Name

Initial

Value

R/W

Description

15 to 8



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

CDA1

CDA0

R/W

L Bus Cycle/I Bus Cycle Select A

Select the L bus cycle or I bus cycle as the bus cycle of

the channel A break condition.

00: Condition comparison is not performed

01: The break condition is the L bus cycle

10: The break condition is the I bus cycle

11: The break condition is the L bus cycle

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