SH7713 datasheet(324/904 Pages) RENESAS

324 / 904 page

Section 9 User Break Controller

Rev.1.50 Aug. 30, 2006 Page 284 of 860

REJ09B0288-0150

Table 9.3

Data Access Cycle Addresses and Operand Size Comparison Conditions

Access Size

Address Compared

Longword

Compares break address register bits 31 to 2 to address bus bits 31 to 2

Word

Compares break address register bits 31 to 1 to address bus bits 31 to 1

Byte

Compares break address register bits 31 to 0 to address bus bits 31 to 0

This means that when address H'00001003 is set in the break address register (BARA or

BARB), for example, the bus cycle in which the break condition is satisfied is as follows

(where other conditions are met).

Longword access at H'00001000

Word access at H'00001002

Byte access at H'00001003

3. When the data value is included in the break conditions on channel B:

When the data value is included in the break conditions, either longword, word, or byte is

specified as the operand size of the break bus cycle register B (BBRB). When data values are

included in break conditions, a break is generated when the address conditions and data

conditions both match. To specify byte data for this case, set the same data in two bytes at bits

15 to 8 and bits 7 to 0 of the break data register B (BDRB) and break data mask register B

(BDMRB). When word or byte is set, bits 31 to 16 of BDRB and BDMRB are ignored. Set the

word data in bits 31 to 16 in BDRB and BDMRB when including the value of the data bus as a

break condition for the MOVS.W @-As,Ds, MOVS.W @As,Ds, MOVS.W @As+,Ds, or

MOVS.W @As+Ix,Ds instruction (bits 15 to 0 are ignored).

4. Access by a PREF instruction is handled as read access in longword units without access data.

Therefore, if including the value of the data bus when a PREF instruction is specified as a

break condition, a break will not occur.

5. If the L bus is selected, a break occurs on ending execution of the instruction that matches the

break condition, and immediately before the next instruction is executed. However, when data

is also specified as the break condition, the break may occur on ending execution of the

instruction following the instruction that matches the break condition. If the I bus is selected,

the instruction at which the break will occur cannot be determined. When this kind of break

occurs at a delayed branch instruction or its delay slot, the break may not actually take place

until the first instruction at the branch destination.

SH7713 Datasheet(PDF) 324 Page - Renesas Technology Corp