SH7713 datasheet(328/904 Pages) RENESAS

328 / 904 page

Section 9 User Break Controller

Rev.1.50 Aug. 30, 2006 Page 288 of 860

REJ09B0288-0150

Bus cycle: L bus/instruction fetch (before instruction execution)/read (operand size is not

included in the condition)

The ASID check is not included.

A user break occurs after an instruction of address H'00000404 is executed or before

instructions of addresses H'00008010 to H'00008016 are executed.

• Register specifications

BARA = H'00037226, BAMRA = H'00000000, BBRA = H'0056, BARB = H'0003722E,

BAMRB = H'00000000, BBRB = H'0056, BDRB = H'00000000, BDMRB = H'00000000,

BRCR = H'00000008, BASRA = H'80, BASRB = H'70

Specified conditions: Channel A/channel B sequential mode

Address:

H'00037226, Address mask: H'00000000, ASID = H'80

Bus cycle: L bus/instruction fetch (before instruction execution)/read/word

Address:

H'0003722E, Address mask: H'00000000, ASID = H'70

Data:

H'00000000, Data mask: H'00000000

Bus cycle: L bus/instruction fetch (before instruction execution)/read/word

After an instruction with ASID = H’80 and address H'00037226 is executed, a user break

occurs before an instruction with ASID = H’70 and address H'0003722E is executed.

• Register specifications

BARA = H'00027128, BAMRA = H'00000000, BBRA = H'005A, BARB = H'00031415,

BAMRB = H'00000000, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000,

BRCR = H'00300000

Specified conditions: Channel A/channel B independent mode

Address:

H'00027128, Address mask: H'00000000

Bus cycle: L bus/instruction fetch (before instruction execution)/write/word

The ASID check is not included.

Address:

H'00031415, Address mask: H'00000000

Data:

H'00000000, Data mask: H'00000000

The ASID check is not included.

Bus cycle: L bus/instruction fetch (before instruction execution)/read (operand size is not

included in the condition)

SH7713 Datasheet(PDF) 328 Page - Renesas Technology Corp