SH7713 datasheet(331/904 Pages) RENESAS

331 / 904 page

Section 9 User Break Controller

Rev.1.50 Aug. 30, 2006 Page 291 of 860

REJ09B0288-0150

• Register specifications

BARA = H'01000000, BAMRA = H'00000000, BBRA = H'0066, BARB = H'0000F000,

BAMRB = H'FFFF0000, BBRB = H'036A, BDRB = H'00004567, BDMRB = H'00000000,

BRCR = H'00300080

Specified conditions: Channel A/channel B independent mode

Address:

H'01000000, Address mask: H'00000000

Bus cycle: L bus/data access/read/word

The ASID check is not included.

Y Address: H'0000F000, Address mask: H'FFFF0000

Data:

H'00004567, Data mask: H'00000000

Bus cycle: Y bus/data access/write/word

The ASID check is not included.

On channel A, a user break occurs during word read from address H'01000000 in the memory

space. On channel B, a user break occurs when word data H'4567 is written in address

H'0000F000 in the Y memory space. The X/Y-memory space is changed by a mode setting.

Break Condition Specified for I Bus Data Access Cycle:

• Register specifications

BARA = H'00314156, BAMRA = H'00000000, BBRA = H'0094, BARB = H'00055555,

BAMRB = H'00000000, BBRB = H'00A9, BDRB = H'00007878, BDMRB = H'00000F0F,

BRCR = H'00000080, BASRA = H'80, BASRB = H'70

Specified conditions: Channel A/channel B independent mode

Address:

H'00314156, Address mask: H'00000000, ASID = H'80

Bus cycle: I bus/instruction fetch/read (operand size is not included in the condition)

Address:

H'00055555, Address mask: H'00000000, ASID = H'70

Data:

H'00000078, Data mask: H'0000000F

Bus cycle: I bus/data access/write/byte

On channel A, a user break occurs when instruction fetch is performed for ASID = H’80 and

address H'00314156 in the memory space.

On channel B, a user break occurs when ASID = H’70 and byte data H'7* is written in address

H'00055555 on the I bus.

SH7713 Datasheet(PDF) 331 Page - Renesas Technology Corp