SH7713 datasheet(329/904 Pages) RENESAS

329 / 904 page

Section 9 User Break Controller

Rev.1.50 Aug. 30, 2006 Page 289 of 860

REJ09B0288-0150

On channel A, no user break occurs since instruction fetch is not a write cycle. On channel B,

no user break occurs since instruction fetch is performed for an even address.

• Register specifications

BARA = H'00037226, BAMRA = H'00000000, BBRA = H'005A, BARB = H'0003722E,

BAMRB = H'00000000, BBRB = H'0056, BDRB = H'00000000, BDMRB = H'00000000,

BRCR = H'00000008, BASRA = H'80, BASRB = H'70

Specified conditions: Channel A/channel B sequential mode

Address:

H'00037226, Address mask: H'00000000, ASID = H'80

Bus cycle: L bus/instruction fetch (before instruction execution)/write/word

Address:

H'0003722E, Address mask: H'00000000, ASID = H'70

Data:

H'00000000, Data mask: H'00000000

Bus cycle: L bus/instruction fetch (before instruction execution)/read/word

Since instruction fetch is not a write cycle on channel A, a sequential condition does not

match. Therefore, no user break occurs.

• Register specifications

BARA = H'00000500, BAMRA = H'00000000, BBRA = H'0057, BARB = H'00001000,

BAMRB = H'00000000, BBRB = H'0057, BDRB = H'00000000, BDMRB = H'00000000,

BRCR = H'00300001, BETR = H'0005

Specified conditions: Channel A/channel B independent mode

Address:

H'00000500, Address mask: H'00000000

Bus cycle: L bus/instruction fetch (before instruction execution)/read/longword

The ASID check is not included.

Address:

H'00001000, Address mask: H'00000000

Data:

H'00000000, Data mask: H'00000000

Bus cycle: L bus/instruction fetch (before instruction execution)/read/longword

The number of execution-times break enable (5 times)

The ASID check is not included.

On channel A, a user break occurs before an instruction of address H'00000500 is executed.

On channel B, a user break occurs after the instruction of address H'00001000 are executed

four times and before the fifth time.

SH7713 Datasheet(PDF) 329 Page - Renesas Technology Corp