SH7713 datasheet(330/904 Pages) RENESAS

330 / 904 page

Section 9 User Break Controller

Rev.1.50 Aug. 30, 2006 Page 290 of 860

REJ09B0288-0150

• Register specifications

BARA = H'00008404, BAMRA = H'00000FFF, BBRA = H'0054, BARB = H'00008010,

BAMRB = H'00000006, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000,

BRCR = H'00000400, BASRA = H'80, BASRB = H'70

Specified conditions: Channel A/channel B independent mode

Address:

H'00008404, Address mask: H'00000FFF, ASID = H'80

Bus cycle: L bus/instruction fetch (after instruction execution)/read (operand size is not

included in the condition)

Address:

H'00008010, Address mask: H'00000006, ASID = H'70

Data:

H'00000000, Data mask: H'00000000

Bus cycle: L bus/instruction fetch (before instruction execution)/read (operand size is not

included in the condition)

A user break occurs after an instruction with ASID = H’80 and addresses H'00008000 to

H'00008FFE is executed or before an instruction with ASID = H’70 and addresses H'00008010

to H'00008016 are executed.

Break Condition Specified for L Bus Data Access Cycle:

• Register specifications

BARA = H'00123456, BAMRA = H'00000000, BBRA = H'0064, BARB = H'000ABCDE,

BAMRB = H'000000FF, BBRB = H'006A, BDRB = H'0000A512, BDMRB = H'00000000,

BRCR = H'00000080, BASRA = H'80, BASRB = H'70

Specified conditions: Channel A/channel B independent mode

Address:

H'00123456, Address mask: H'00000000, ASID = H’80

Bus cycle: L bus/data access/read (operand size is not included in the condition)

Address:

H'000ABCDE, Address mask: H'000000FF, ASID = H’70

Data:

H'0000A512, Data mask: H'00000000

Bus cycle: L bus/data access/write/word

On channel A, a user break occurs with longword read from ASID = H’80 and address

H'00123454, word read from address H'00123456, or byte read from address H'00123456. On

channel B, a user break occurs when word H'A512 is written in ASID = H’70 and addresses

H'000ABC00 to H'000ABCFE.

SH7713 Datasheet(PDF) 330 Page - Renesas Technology Corp