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SH7721 Datasheet(PDF) 468 Page - Renesas Technology Corp |
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SH7721 Datasheet(HTML) 468 Page - Renesas Technology Corp |
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468 / 1524 page ![]() Section 9 Bus State Controller (BSC) Rev. 3.00 Jan. 18, 2008 Page 406 of 1458 REJ09B0033-0300 (3) On-Chip Peripheral Module Access To access an on-chip module register, two or more peripheral module clock (P φ) cycles are required. Care must be taken in system design. (4) External Bus Priority Order Access via an external bus is performed in the priority order below: BREQ > Refresh > LCDC > USBH > DMAC > CPU Note that next transfer is not performed until current transfer (e.g. burst transfer) has completed. |
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