SH7721 datasheet(469/1524 Pages) RENESAS

469 / 1524 page

Section 10

Direct Memory Access Controller (DMAC)

DMAS301A_010020030200

Rev. 3.00 Jan. 18, 2008 Page 407 of 1458

REJ09B0033-0300

Section 10

Direct Memory Access Controller (DMAC)

This LSI includes the direct memory access controller (DMAC).

The DMAC can be used in place of the CPU to perform high-speed transfers between external

devices that have DACK (transfer request acknowledge signal), external memory, on-chip

memory, memory-mapped external devices, and on-chip peripheral modules.

10.1

Features

• Six channels (two channels can receive an external request)

• 4-Gbyte physical address space

• Data transfer unit is selectable: Byte, word (2 bytes), longword (4 bytes), and 16 bytes

(longword

× 4)

• Maximum transfer count: 16,777,216 transfers

• Address mode: Dual address mode or single address mode can be selected.

• Transfer requests:

External request, on-chip peripheral module request, or auto request can be selected.

The following modules can issue an on-chip peripheral module request.

 SCIF0, SIOF1, MMC, CMT (channels 0 to 4), SIM, USBF, SIOF0, SIOF1, ADC, and

SDHI

• Selectable bus modes:

Cycle steal mode (normal mode and intermittent mode) or burst mode can be selected.

• Selectable channel priority levels:

The channel priority levels are selectable between fixed mode and round-robin mode.

• Interrupt request: An interrupt request can be generated to the CPU after transfers end by the

specified counts.

• External request detection: There are following four types of DREQ input detection.

 Low level detection

 High level detection

 Rising edge detection

 Falling edge detection

• Transfer request acknowledge signal:

Active levels for DACK and TEND can be set independently.

SH7721 Datasheet(PDF) 469 Page - Renesas Technology Corp