SH7721 datasheet(470/1524 Pages) RENESAS

Part #	SH7721

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	1524 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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470 / 1524 page

Section 10

Direct Memory Access Controller (DMAC)

Rev. 3.00 Jan. 18, 2008 Page 408 of 1458

REJ09B0033-0300

Figure 10.1 shows the block diagram of the DMAC.

SARn

DMAC module

Iteration

control

Start-up

control

Request

priority

control

Bus

interface

DARn

DMATCRn

CHCRn

DMAOR

DMARS0 to

DMARS2

DEIn

DACK0, DACK1

TEND0, TEND1

DREQ0, DREQ1

External

ROM

External

RAM

External

I/O (memory

mapped)

External

I/O (with

acknowledge-

ment)

Bus state

controller

On-chip

memory

On-chip peripheral

module

SARn:

DARn:

DMATCRn:

CHCRn:

DMAOR:

DMARS0 to

DMARS2:

DEIn:

DMA source address register

DMA destination address register

DMA transfer count register

DMA channel control register

DMA operation register

DMA extended resource selector 0 to 2

DMA transfer-end interrupt request to the CPU

0, 1, 2, 3, 4, 5

[Legend]

DMA transfer

request signal

DMA transfer acknowledge signal

Interrupt controller

Figure 10.1

Block Diagram of DMAC

SH7721 Datasheet(PDF) 470 Page - Renesas Technology Corp

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