SH7721 datasheet(474/1524 Pages) RENESAS

474 / 1524 page

Section 10

Direct Memory Access Controller (DMAC)

Rev. 3.00 Jan. 18, 2008 Page 412 of 1458

REJ09B0033-0300

10.3.2

DMA Destination Address Registers (DAR_0 to DAR_5)

DAR are 32-bit readable/writable registers that specify the destination address of a DMA transfer.

During a DMA transfer, these registers indicate the next destination address. When the data is

transferred from an external device with the DACK in single address mode, the DAR is ignored.

To transfer data in 16 bits or in 32 bits, specify the address with 16-bit or 32-bit address boundary.

When transferring data in 16-byte units, a 16-byte boundary must be set for the destination address

value. The initial value is undefined.

10.3.3

DMA Transfer Count Registers (DMATCR_0 to DMATCR_5)

DMATCR are 32-bit readable/writable registers that specify the DMA transfer count. The number

of transfers is 1 when the setting is H'00000001, 16,777,215 when H'00FFFFFF is set, and

16,777,216 (the maximum) when H'00000000 is set. During a DMA transfer, these registers

indicate the remaining transfer count.

The upper eight bits of DMATCR are always read as 0, and the write value should always be 0. To

transfer data in 16 bytes, one 16-byte transfer (128 bits) counts one. The initial value is undefined.

SH7721 Datasheet(PDF) 474 Page - Renesas Technology Corp