SH7721 datasheet(476/1524 Pages) RENESAS

476 / 1524 page

Section 10

Direct Memory Access Controller (DMAC)

Rev. 3.00 Jan. 18, 2008 Page 414 of 1458

REJ09B0033-0300

Bit

Bit Name

Initial

Value

R/W

Descriptions

R/W

Acknowledge Level

Specifies whether the DACK signal output is high active

or low active.

This bit is valid only in CHCR_0 and CHCR_1. This bit

is always reserved and read as 0 in CHCR_2 to

CHCR_5. The write value should always be 0.

0: Low-active output of DACK

1: High-active output of DACK

DM1

DM0

R/W

Destination Address Mode 1, 0

Specify whether the DMA destination address is

incremented, decremented, or left fixed. (In single

address mode, the DM1 and DM0 bits are ignored

when data is transferred to an external device with

DACK.)

00: Fixed destination address (setting prohibited in 16-

byte transfer)

01: Destination address is incremented (+1 in byte-unit

transfer, +2 in word-unit transfer, +4 in longword-

unit transfer, +16 in 16-byte transfer)

10: Destination address is decremented (–1 in byte-unit

transfer, –2 in word-unit transfer, –4 in longword-

unit transfer; setting prohibited in 16-byte transfer)

11: Setting prohibited

SM1

SM0

R/W

Source Address Mode 1, 0

Specify whether the DMA source address is

incremented, decremented, or left fixed. (In single

address mode, SM1 and SM0 bits are ignored when

data is transferred from an external device with DACK.)

00: Fixed source address (setting prohibited in 16-byte

transfer)

01: Source address is incremented (+1 in byte-unit

transfer, +2 in word-unit transfer, +4 in longword-

unit transfer, +16 in 16-byte transfer)

10: Source address is decremented (–1 in byte-unit

transfer, –2 in word-unit transfer, –4 in longword-

unit transfer; setting prohibited in 16-byte transfer)

11: Setting prohibited

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