SH7721 datasheet(480/1524 Pages) RENESAS

480 / 1524 page

Section 10

Direct Memory Access Controller (DMAC)

Rev. 3.00 Jan. 18, 2008 Page 418 of 1458

REJ09B0033-0300

10.3.5

DMA Operation Register (DMAOR)

DMAOR is a 16-bit readable/writable register that specifies the priority level of channels at the

DMA transfer. This register shows the DMA transfer status.

Bit

Bit Name

Initial

Value

R/W

Description

15, 14



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

CMS1

CMS0

R/W

Cycle Steal Mode Select 1, 0

Select either normal mode or intermittent mode in cycle

steal mode.

It is necessary that all channel's bus modes are set to

cycle steal mode to make valid intermittent mode.

00: Normal mode

01: Setting prohibited

10: Intermittent mode 16

Executes one DMA transfer in each of 16 clocks of an

external bus clock.

11: Intermittent mode 64

Executes one DMA transfer in each of 64 clocks of an

external bus clock.

11, 10



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

PR1

PR0

R/W

Priority Mode 1, 0

Select the priority level between channels when there are

transfer requests for multiple channels simultaneously.

00: CH0 > CH1 > CH2 > CH3 > CH4 > CH5

01: CH0 > CH2 > CH3 > CH1 > CH4 > CH5

10: Setting prohibited

11: Round-robin mode

7 to 3



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

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