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SH7721 Datasheet(PDF) 484 Page - Renesas Technology Corp |
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SH7721 Datasheet(HTML) 484 Page - Renesas Technology Corp |
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484 / 1524 page ![]() Section 10 Direct Memory Access Controller (DMAC) Rev. 3.00 Jan. 18, 2008 Page 422 of 1458 REJ09B0033-0300 • DMARS2 Bit Bit Name Initial Value R/W Description 15 14 13 12 11 10 C5MID5 C5MID4 C5MID3 C5MID2 C5MID1 C5MID0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Transfer request module ID5 to ID0 for DMA channel 5 (MID) See table 10.2. 9 8 C5RID1 C5RID0 0 0 R/W R/W Transfer request register ID1 and ID0 for DMA channel 5 (RID) See table 10.2. 7 6 5 4 3 2 C4MID5 C4MID4 C4MID3 C4MID2 C4MID1 C4MID0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Transfer request module ID5 to ID0 for DMA channel 4 (MID) See table 10.2. 1 0 C4RID1 C4RID0 0 0 R/W R/W Transfer request register ID1 and ID0 for DMA channel 4 (RID) See table 10.2. |
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