SH7721 datasheet(487/1524 Pages) RENESAS

Part #	SH7721

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	1524 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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487 / 1524 page

Section 10

Direct Memory Access Controller (DMAC)

Rev. 3.00 Jan. 18, 2008 Page 425 of 1458

REJ09B0033-0300

Figure 10.2 shows a flowchart of this procedure.

Normal end

NMIF = 1

or AE = 1 or DE = 0

or DME = 0?

Bus mode,

transfer request mode,

DREQ detection selection

system

Initial settings

(SAR, DAR, DMATCR, CHCR, DMAOR, DMARS)

Transfer (1 transfer unit);

DMATCR – 1

→ DMATCR, SAR and DAR

updated

DEI interrupt request (when IE = 1)

TE = 1

Yes

Start

Transfer aborted

DMATCR = 0?

Transfer request

occurs?*1

DE, DME = 1 and

NMIF, AE, TE = 0?

NMIF = 1

or AE = 1 or DE = 0

or DME = 0?

Transfer end

Notes: 1. In auto-request mode, transfer begins when the NMIF, AE, and TE bits are all 0 and the DE and

DME bits are set to 1.

2. DREQ = level detection in burst mode (external request) or cycle-steal mode.

3. DREQ = edge detection in burst mode (external request), or auto-request mode in burst mode.

Figure 10.2

DMA Transfer Flowchart

SH7721 Datasheet(PDF) 487 Page - Renesas Technology Corp