SH7721 datasheet(486/1524 Pages) RENESAS

486 / 1524 page

Section 10

Direct Memory Access Controller (DMAC)

Rev. 3.00 Jan. 18, 2008 Page 424 of 1458

REJ09B0033-0300

10.4

Operation

When there is a DMA transfer request, the DMAC starts the transfer according to the

predetermined channel priority; when the transfer end conditions are satisfied, it ends the transfer.

Transfers can be requested in three modes: auto request, external request, and on-chip peripheral

module request. In bus mode, burst mode or cycle steal mode can be selected.

10.4.1

DMA Transfer Flow

After the DMA source address registers (SAR), DMA destination address registers (DAR), DMA

transfer count registers (DMATCR), DMA channel control registers (CHCR), DMA operation

data according to the following procedure:

1. Checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0)

2. When a transfer request occurs while transfer is enabled, the DMAC transfers one transfer unit

of data (depending on the TS0 and TS1 settings). In auto request mode, the transfer begins

automatically when the DE bit and DME bit are set to 1. The DMATCR value will be

decremented for each transfer. The actual transfer flows vary by address mode and bus mode.

3. When the specified number of transfer have been completed (when DMATCR reaches 0), the

transfer ends normally. If the IE bit in CHCR is set to 1 at this time, a DEI interrupt is sent to

the CPU.

4. When an address error or an NMI interrupt is generated, the transfer is aborted. Transfers are

also aborted when the DE bit in CHCR or the DME bit in DMAOR is changed to 0.

SH7721 Datasheet(PDF) 486 Page - Renesas Technology Corp