SH7721 datasheet(489/1524 Pages) RENESAS

489 / 1524 page

Section 10

Direct Memory Access Controller (DMAC)

Rev. 3.00 Jan. 18, 2008 Page 427 of 1458

REJ09B0033-0300

Choose to detect DREQ by either the edge or level of the signal input with the DL bit and DS bit

in CHCR_0 and CHCR_1 as shown in table 10.4. The source of the transfer request does not have

to be the data transfer source or destination.

Table 10.4

Selecting External Request Detection with DL, DS Bits

CHCR_0 or CHCR_1

Detection of External Request

Low level detection

Falling edge detection

High level detection

Rising edge detection

When DREQ is accepted, the DREQ pin becomes request accept disabled state. After issuing

acknowledge signal DACK for the accepted DREQ, the DREQ pin again becomes request accept

enabled state.

When DREQ is used by level detection, there are following two cases by the timing to detect the

next DREQ after outputting DACK.

• Overrun 0: Transfer is aborted after the same number of transfer has been performed as

requests.

• Overrun 1: Transfer is aborted after transfers have been performed for (the number of requests

plus 1) times.

The DO bit in CHCR selects this overrun 0 or overrun 1.

Table 10.5

Selecting External Request Detection with DO Bit

CHCR_0 or CHCR_1

External Request

Overrun 0

Overrun 1

SH7721 Datasheet(PDF) 489 Page - Renesas Technology Corp