SH7721 datasheet(488/1524 Pages) RENESAS

488 / 1524 page

Section 10

Direct Memory Access Controller (DMAC)

Rev. 3.00 Jan. 18, 2008 Page 426 of 1458

REJ09B0033-0300

10.4.2

DMA Transfer Requests

DMA transfer requests are basically generated in either the data transfer source or destination, but

they can also be generated by external devices or on-chip peripheral modules that are neither the

source nor the destination. Transfers can be requested in three modes: auto request, external

request, and on-chip peripheral module request. The request mode is selected in the RS3 to RS0

bits in CHCR0 to CHCR3, and DMARS0 to DMARS2.

(1)

Auto-Request Mode

When there is no transfer request signal from an external source, as in a memory-to-memory

transfer or a transfer between memory and an on-chip peripheral module unable to request a

transfer, auto-request mode allows the DMAC to automatically generate a transfer request signal

internally. When the DE bits in CHCR and the DME bit in DMAOR are set to 1, the transfer

begins so long as the AE and NMIF bits in DMAOR are all 0.

(2)

External Request Mode

In this mode, a transfer is performed at the request signals (DREQ0 and DREQ1) of an external

device. This mode is valid only in channel 0 and channel 1. Choose one of the modes shown in

table 10.3 according to the application system. When this mode is selected, if the DMA transfer is

enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0), a transfer is performed upon a request at

the DREQ input.

Table 10.3

Selecting External Request Modes with RS Bits

RS3

RS2

RS1

RS0

Address Mode

Source

Destination

Dual address

mode

Any

External memory,

memory-mapped

external device

External device with

DACK

Single address

mode

External device with

DACK

External memory,

memory-mapped

external device

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