SH7721 datasheet(479/1524 Pages) RENESAS

479 / 1524 page

Section 10

Direct Memory Access Controller (DMAC)

Rev. 3.00 Jan. 18, 2008 Page 417 of 1458

REJ09B0033-0300

Bit

Bit Name

Initial

Value

R/W

Descriptions

R/(W)* Transfer End Flag

Shows that DMA transfer ends. The TE bit is set to 1

when data transfer ends when DMATCR becomes to 0.

The TE bit is not set to 1 in the following cases.

• DMA transfer ends due to an NMI interrupt or DMA

address error before DMATCR is cleared to 0.

• DMA transfer is ended by clearing the DE bit and

DME bit in the DMA operation register (DMAOR).

To clear the TE bit, the TE bit should be written to 0 after

reading 1.

Even if the DE bit is set to 1 while this bit is set to 1,

transfer is not enabled.

0: During the DMA transfer or DMA transfer has been

interrupted

[Clearing condition]

Writing 0 after TE = 1 read

1: DMA transfer ends by the specified count (DMATCR =

R/W

DMA Enable

Enables or disables the DMA transfer. In auto request

mode, DMA transfer starts by setting the DE bit and DME

bit in DMAOR to 1. In this time, all of the bits TE, NMIF,

and AE in DMAOR must be 0. In an external request or

peripheral module request, DMA transfer starts if DMA

transfer request is generated by the devices or peripheral

modules after setting the bits DE and DME to 1. In this

case, however, all of the bits TE, NMIF, and AE must be

0, which is the same as in the case of auto request

mode. Clearing the DE bit to 0 can terminate the DMA

transfer.

0: DMA transfer disabled

1: DMA transfer enabled

Note:

Writing 0 is possible to clear the flag.

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