SH7721 datasheet(478/1524 Pages) RENESAS

478 / 1524 page

Section 10

Direct Memory Access Controller (DMAC)

Rev. 3.00 Jan. 18, 2008 Page 416 of 1458

REJ09B0033-0300

Bit

Bit Name

Initial

Value

R/W

Descriptions

R/W

DREQ Level and DREQ Edge Select

Specify the detecting method of the DREQ pin input and

the detecting level.

These bits are valid only in CHCR_0 and CHCR_1.

These bits are always reserved and read as 0 in CHCR_2

to CHCR_5. The write value should always be 0.

In channels 0 and 1, also, if the transfer request source is

specified as an on-chip peripheral module or if an auto-

request is specified, these bits are invalid.

00: DREQ detected in low level

01: DREQ detected at falling edge

10: DREQ detected in high level

11: DREQ detected at rising edge

R/W

Transfer Bus Mode

Specifies the bus mode when DMA transfers data.

0: Cycle steal mode

1: Burst mode

TS1

TS0

R/W

Transfer Size 1, 0

Specify the size of data to be transferred.

Select the size of data to be transferred when the source

or destination is an on-chip peripheral module register of

which transfer size is specified.

00: Byte size

01: Word size (2 bytes)

10: Longword size (4 bytes)

11: 16-byte unit (four longword transfers)

R/W

Interrupt Enable

Specifies whether or not an interrupt request is generated

to the CPU at the end of the DMA transfer. Setting this bit

to 1 generates an interrupt request (DEI) to the CPU

when the TE bit is set to 1.

0: Interrupt request is disabled.

1: Interrupt request is enabled.

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