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SH7721 Datasheet(PDF) 508 Page - Renesas Technology Corp |
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SH7721 Datasheet(HTML) 508 Page - Renesas Technology Corp |
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508 / 1524 page  Section 10 Direct Memory Access Controller (DMAC) Rev. 3.00 Jan. 18, 2008 Page 446 of 1458 REJ09B0033-0300 CKIO DACK (High-active) CPU CPU DMAC CKIO DACK (High-active) CPU CPU DMAC DMAC Bus cycle DREQ (Overrun 0, high-level) Bus cycle DREQ (Overrun 1, high-level) Non-sensitive period Non-sensitive period 1st acceptance 1st acceptance 3rd acceptance 2nd acceptance Acceptance started Acceptance started Acceptance started 2nd acceptance Figure 10.16 Example of DREQ Input Detection in Burst Mode Level Detection DMAC CPU CPU CPU DMAC CKIO DREQ DACK TEND Bus cycle Last DMA transfer Figure 10.17 Example of DMA Transfer End in Cycle Steal Mode Level Detection |
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