SH7721 datasheet(505/1524 Pages) RENESAS

505 / 1524 page

Section 10

Direct Memory Access Controller (DMAC)

Rev. 3.00 Jan. 18, 2008 Page 443 of 1458

REJ09B0033-0300

(4)

Bus Mode and Channel Priority

When the priority is set in fixed mode (CH0 > CH1), even though channel 1 is transferring in burst

mode, if there is a transfer request to channel 0 which has a higher priority, the transfer of channel

0 will begin immediately.

At this time, if channel 0 is also operating in burst mode, the channel 1 transfer will continue when

the channel 0 transfer with a higher priority has completely finished.

If channel 0 is operating in cycle steal mode, immediately after channel 0 with a higher priority

completes the transfer of one transfer unit, the channel 1 transfer will begin again without

releasing the bus mastership. Transfer will then switch between the two in the order of channel 0,

channel 1, channel 0, and channel 1. For the bus state, the CPU cycle after cycle steal mode

transfer finishes is replaced with a burst mode transfer cycle (hereafter referred to as burst mode

high-priority execution).

This example is illustrated in figure 10.12. If there are channels with conflicting burst transfers,

transfer for the channel with the highest priority is performed first.

In DMA transfer for more than one channel, the DMAC does not give the bus mastership to the

bus master until all conflicting burst transfers have finished.

CPU

DMA

CH1

DMA

CH1

DMA

CH0

DMA

CH1

DMA

CH0

DMA

CH1

DMA

CH1

CPU

CH0

CH1

CH0

DMAC CH0 and CH1

Cycle-steal mode

DMAC CH1

Burst mode

CPU

Priority: CH0 > CH1

CH0: Cycle-steal mode

CH1: Burst mode

DMAC CH1

Burst mode

Figure 10.12

Bus State when Multiple Channels are Operating

In round-robin mode, the priority changes according to the specifications shown in figure 10.3.

Note that a channel operating in cycle steal mode cannot be handled together with a channel

operating in burst mode.

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