SH7721 datasheet(502/1524 Pages) RENESAS

502 / 1524 page

Section 10

Direct Memory Access Controller (DMAC)

Rev. 3.00 Jan. 18, 2008 Page 440 of 1458

REJ09B0033-0300

This intermittent mode can be used for all transfer section; transfer request source, transfer

source, and transfer destination. The bus modes, however, must be cycle steal mode in all

channels.

Figure 10.10 shows an example of DMA transfer timing in cycle steal intermittent mode.

Transfer conditions shown in the figure are:

 Dual address mode

 DREQ low level detection

DREQ

CPU

Bus cycle

CPU

More than 16 or 64 B

(change by the CPU, LCDC, and USBH states of using bus)

DMAC DMAC

CPU

DMAC DMAC

CPU

Read/Write

Figure 10.10

Example of DMA Transfer in Cycle Steal Intermittent Mode

(Dual Address, DREQ Low Level Detection)

(b)

Burst Mode

In burst mode, once the DMAC obtains the bus mastership, the transfer is performed continuously

without releasing the bus mastership until the transfer end condition is satisfied. In external

request mode with level detection of the DREQ pin, however, when the DREQ pin is not active,

the bus mastership passes to the other bus master after the DMAC transfer request that has already

been accepted ends, even if the transfer end conditions have not been satisfied.

Burst mode cannot be used for other than CMT (channels 0 to 4) when the on-chip peripheral

module is the transfer request source.

Figure 10.11 shows DMA transfer timing in burst mode.

CPU

DMAC DMAC DMAC

DMAC

DMAC DMAC

CPU

DREQ

Bus cycle

Read

Write

Figure 10.11

DMA Transfer Example in Burst Mode

(Dual Address, DREQ Low Level Detection)

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