SH7721 datasheet(501/1524 Pages) RENESAS

501 / 1524 page

Section 10

Direct Memory Access Controller (DMAC)

Rev. 3.00 Jan. 18, 2008 Page 439 of 1458

REJ09B0033-0300

(2)

Bus Modes

There are two bus modes: cycle steal mode and burst mode. Select the mode in the TB bits in the

channel control register (CHCR).

(a)

Cycle-Steal Mode

• Normal mode

In cycle-steal normal mode, the bus mastership is given to another bus master after a one-

transfer-unit (byte, word, longword, or 16-byte unit) DMA transfer. When another transfer

request occurs, the bus mastership is obtained from the other bus master and a transfer is

performed for one transfer unit. When that transfer ends, the bus mastership is passed to the

other bus master. This is repeated until the transfer end conditions are satisfied.

In cycle-steal normal mode, transfer areas are not affected regardless of settings of the transfer

request source, transfer source, and transfer destination.

Figure 10.9 shows an example of DMA transfer timing in cycle-steal normal mode. Transfer

conditions shown in the figure are:

 Dual address mode

 DREQ low level detection

CPU

DMAC

CPU

DMAC

CPU

DREQ

Bus cycle

Bus mastership returned to CPU once

Read/Write

Figure 10.9

DMA Transfer Example in Cycle-Steal Normal Mode

(Dual Address, DREQ Low Level Detection)

• Intermittent mode 16 and intermittent mode 64

In intermittent mode of cycle steal, the DMAC returns the bus mastership to other bus master

whenever a unit of transfer (byte, word, longword, or 16-byte unit) is complete. If the next

transfer request occurs after that, the DMAC gets the bus mastership from other bus master

after waiting for 16 or 64 clocks in B

φ count. The DMAC then transfers data of one unit and

returns the bus mastership to other bus master. These operations are repeated until the transfer

end condition is satisfied. It is thus possible to make lower the ratio of bus occupation by DMA

transfer than cycle-steal normal mode.

When the DMAC gets again the bus mastership, DMA transfer can be postponed in case of

entry updating due to cache miss.

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