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SH7721 Datasheet(PDF) 497 Page - Renesas Technology Corp |
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SH7721 Datasheet(HTML) 497 Page - Renesas Technology Corp |
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497 / 1524 page ![]() Section 10 Direct Memory Access Controller (DMAC) Rev. 3.00 Jan. 18, 2008 Page 435 of 1458 REJ09B0033-0300 (1) Address Modes (a) Dual Address Mode In dual address mode, both the transfer source and destination are accessed by an address. The source and destination can be located externally or internally. DMA transfer requires two bus cycles because data is read from the transfer source in a data read cycle and written to the transfer destination in a data write cycle. At this time, transfer data is temporarily stored in the DMAC. In the transfer between external memories as shown in figure 10.5, data is read to the DMAC from one external memory in a data read cycle, and then that data is written to the other external memory in a write cycle. Data buffer Memory Transfer source module Transfer destination module Memory Transfer source module Transfer destination module SAR DAR Data buffer SAR DAR The SAR value is an address, data is read from the transfer source module, and the data is temporarily stored in the DMAC. First bus cycle Second bus cycle The DAR value is an address and the value stored in the data buffer in the DMAC is written to the transfer destination module. DMAC DMAC Figure 10.5 Data Flow of Dual Address Mode Auto request, external request, and on-chip peripheral module request are available for the transfer request. DACK can be output in read cycle or write cycle in dual address mode. The channel control register (CHCR) can specify whether the DACK is output in read cycle or write cycle. |
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