SH7721 datasheet(494/1524 Pages) RENESAS

494 / 1524 page

Section 10

Direct Memory Access Controller (DMAC)

Rev. 3.00 Jan. 18, 2008 Page 432 of 1458

REJ09B0033-0300

CH1

> CH2 > CH3 > CH4 > CH5 > CH0

CH0

> CH1 > CH2 > CH3 > CH4 > CH5

CH2

> CH3 > CH4 > CH5 > CH0 > CH1

CH0

> CH1 > CH2 > CH3 > CH4 > CH5

CH0

> CH1 > CH2 > CH3 > CH4 > CH5

CH0

> CH1 > CH2 > CH3 > CH4 > CH5

CH0

> CH1 > CH2 > CH3 > CH4 > CH5

CH3

> CH4 > CH5 > CH0 > CH1 > CH2

CH0

> CH1 > CH2 > CH3 > CH4 > CH5

(1) When channel 0 transfers

Initial priority order

Priority order

after transfer

Priority order does not change.

Channel 2 becomes bottom

priority.

The priority of channels 0 and 1,

which were higher than channel 2,

are also shifted. If immediately

after there is a request to transfer

channel 5 only, channel 5 becomes

bottom priority and the priority of

channels 3 and 4, which were

higher than channel 5, are also

shifted.

Channel 1 becomes bottom

priority.

The priority of channel 0, which

was higher than channel 1, is also

shifted.

Channel 0 becomes bottom

priority

Priority order

after transfer

Priority order

after transfer

Priority order

after transfer

Post-transfer priority order

when there is an

immediate transfer

request to channel 5 only

(2) When channel 1 transfers

(3) When channel 2 transfers

(4) When channel 5 transfers

Figure 10.3

Round-Robin Mode

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