SH7721 datasheet(503/1524 Pages) RENESAS

503 / 1524 page

Section 10

Direct Memory Access Controller (DMAC)

Rev. 3.00 Jan. 18, 2008 Page 441 of 1458

REJ09B0033-0300

(3)

Relationship between Request Modes and Bus Modes by DMA Transfer Category

Table 10.8 shows the relationship between request modes and bus modes by DMA transfer

category.

Table 10.8

Relationship between Request Modes and Bus Modes by DMA Transfer

Category

Address

Mode

Transfer Category

Request

Mode

Bus

Mode

Transfer

Size (Bits)

Usable

Channels

External device with DACK and external

memory

External

B/C

8/16/32/128

0,1

External device with DACK and memory-

mapped external device

External

B/C

8/16/32/128

0, 1

External memory and external memory

All*

B/C

8/16/32/128

0 to 5*

External memory and memory-mapped

external device

All*

B/C

8/16/32/128

0 to 5*

Memory-mapped external device and

memory-mapped external device

All*

B/C

8/16/32/128

0 to 5*

External memory and on-chip peripheral

module

All*

B/C*

8/16/32/128*

0 to 5*

Memory-mapped external device and

on-chip peripheral module

All*

B/C*

8/16/32/128*

0 to 5*

On-chip peripheral module and on-chip

peripheral module

All*

B/C*

8/16/32/128*

0 to 5*

X/Y memory and X/Y memory

All*

B/C

8/16/32/128

0 to 5*

X/Y memory and memory-mapped

external device

All*

B/C

8/16/32/128

0 to 5*

X/Y memory and on-chip peripheral

module

All*

B/C*

8/16/32/128*

0 to 5*

Dual

X/Y memory and external memory

All*

B/C

8/16/32/128

0 to 5*

External device with DACK and external

memory

External

B/C

8/16/32

0, 1

Single

External device with DACK and memory-

mapped external device

External

B/C

8/16/32

0, 1

B: Burst mode, C: Cycle steal mode

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