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SH7721 Datasheet(PDF) 507 Page - Renesas Technology Corp |
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SH7721 Datasheet(HTML) 507 Page - Renesas Technology Corp |
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507 / 1524 page ![]() Section 10 Direct Memory Access Controller (DMAC) Rev. 3.00 Jan. 18, 2008 Page 445 of 1458 REJ09B0033-0300 CKIO Bus cycle DREQ (Overrun 0, high-level) Bus cycle DREQ (Overrun 1, high-level) DACK (High-active) CPU CPU CPU DMAC CKIO DACKn (High-active) CPU CPU CPU DMAC Non-sensitive period Non-sensitive period Non-sensitive period 1st acceptance 2nd acceptance 1st acceptance 2nd acceptance Acceptance started Acceptance started Figure 10.14 Example of DREQ Input Detection in Cycle Steal Mode Level Detection CKIO DREQ (Rising edge) DACK (High-active) CPU CPU DMAC DMAC Bus cycle Non-sensitive period Burst acceptance Figure 10.15 Example of DREQ Input Detection in Burst Mode Edge Detection |
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