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SH7721 Datasheet(PDF) 509 Page - Renesas Technology Corp

Part # SH7721
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  1524 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7721 Datasheet(HTML) 509 Page - Renesas Technology Corp

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Section 10
Direct Memory Access Controller (DMAC)
Rev. 3.00 Jan. 18, 2008 Page 447 of 1458
REJ09B0033-0300
When an 8-bit or 16-bit external device is accessed in longword units, or when an 8-bit external
device is accessed in word units, the DACK output is divided because of the data alignment. This
example is illustrated in figure 10.18.
CKIO
CSn
WEn
WAIT
RD
Address
Data
T1
T2
Taw
T1
T2
Note: The DACK is asserted for the last transfer unit
of the DMA transfer. When the transfer unit is
divided into several bus cycles and the
CSn is
negated between bus cycles, the DACK is also
divided.
DACKn
(Active-low)
Figure 10.18
Example of BSC Ordinary Memory Access
(No Wait, Idle Cycle 1, Longword Access to 16-Bit Device)



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