SH7721 datasheet(536/1524 Pages) RENESAS

536 / 1524 page

Section 12 Watchdog Timer (WDT)

Rev. 3.00 Jan. 18, 2008 Page 474 of 1458

REJ09B0033-0300

H'5A

Write data

Address: H'A415FF84

WTCNT write

H'A5

Write data

Address: H'A415FF86

WTCSR write

Figure 12.2 Writing to WTCNT and WTCSR

12.3

WDT Operation

12.3.1

Canceling Software Standbys

The WDT can be used to cancel software standby mode with an NMI interrupt or external

interrupt (IRQ). The procedure is described below. (The WDT does not run when resets are used

for canceling, so keep the

RESETP pin low until the clock stabilizes.)

1. Before transition to software standby mode, always clear the TME bit in WTCSR to 0. When

the TME bit is 1, an erroneous reset or interval timer interrupt may be generated when the

count overflows.

2. Set the type of count clock used in the CKS2 to CKS0 bits in WTCSR and the initial values for

the counter in the WTCNT counter. These values should ensure that the time till count

overflow is longer than the clock oscillation settling time.

3. Move to software standby mode by executing a SLEEP instruction to stop the clock.

4. The WDT starts counting by detecting the edge change of the NMI signal.

5. When the WDT count overflows, the CPG starts supplying the clock and the processor

resumes operation. The WOVF flag in WTCSR is not set when this happens.

6. Since the WDT continues counting from H'00, set the STBY bit in STBCR to 0 in the interrupt

processing program and this will stop the WDT. When the STBY bit remains 1, the LSI again

enters software standby mode when the WDT has counted up to H'80. This software standby

mode can be canceled by a power-on reset.

SH7721 Datasheet(PDF) 536 Page - Renesas Technology Corp