SH7721 datasheet(540/1524 Pages) RENESAS

540 / 1524 page

Section 13

Power-Down Modes

Rev. 3.00

Jan. 18, 2008

Page 478 of 1458

REJ09B0033-0300

Table 13.1 shows the transition conditions for entering the modes from the program execution

state, as well as the CPU and peripheral module states in each mode and the procedures for

canceling each mode.

Table 13.1

States of Power-Down Modes

State

Mode

Transition

Conditions

CPG

CPU

Reg-

ister

On-Chip

Memory

On-Chip

Periphera

l Modules

External

Memory

Canceling

Procedure

Sleep

mode

Execute SLEEP

instruction with

STBY bit in STBCR

cleared to 0

Runs

Halts

Held

Halts

(contents

remained)

Run

Auto-

refreshing

•

Interrupt

•

Reset

Software

Standby

mode

Execute SLEEP

instruction with

STBY bit in STBCR

set to 1

Halts

Held

Halts

(contents

remained)

Halt*

Self-

refreshing

•

Interrupt

(NMI, IRQ

(edge

detection),

RTC, TMU,

PINT

•

Reset

Module

standby

function

Set MSTP bit in

STBCR to 1

Runs

Runs/

halts

Held

Specified

module halts

(contents

remained)

Specified

module

halts

Auto-

refreshing

•

Clear

MSTP bit to

•

Power-on

reset

Hardware

standby

mode

Set CA pin to low

Halts

Held

Halt*

Self-

refreshing

•

Power-on

reset

Note:

The RTC operates when the START bit in RCR2 is set to 1. For details, see section 17,

Realtime Clock (RTC).

13.1.2

Reset

Resetting occurs when power is supplied, and when execution is started again from an initialized

state. There are two types of reset: A power-on reset and a manual reset. In a power-on reset, all

processing in execution is suspended, all unprocessed events are canceled, and reset processing

starts immediately. On the other hand, processing to retain the contents of external memory is

continued in a manual reset. The conditions for generating power-on and manual resets are as

follows.

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