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SH7721 Datasheet(PDF) 559 Page - Renesas Technology Corp |
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SH7721 Datasheet(HTML) 559 Page - Renesas Technology Corp |
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559 / 1524 page  Section 13 Power-Down Modes Rev. 3.00 Jan. 18, 2008 Page 497 of 1458 REJ09B0033-0300 13.8.3 Hardware Standby Mode Timing Figures 13.10 and 13.11 show signal timings in hardware standby mode. Since the signal on the CA pin is sampled at the timing of EXTAL_RTC, clock should be input to the EXTAL_RTC pin when hardware standby mode is entered. In hardware standby mode, the CA pin must be kept low. The clock oscillation starts if the CA pin is pulled high after the RESETP pin is brought low. CKIO CA STATUS normal*3 reset*1 0 to 10 Bcyc standby*2 RESETP Undefined Notes: 1. reset : HH (STATUS1 = High, STATUS0 = High) 2. standby : LHLH (STATUS1 = Low, STATUS0 = High) 3. normal : LL (STATUS1 = Low, STATUS0 = Low) 4. Bcyc : Bus clock cycle Figure 13.10 Hardware Standby Mode Timing (CA is pulled low in normal operation) |
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