SH7721 datasheet(795/1524 Pages) RENESAS

Part #	SH7721

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	1524 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 21

Serial I/O with FIFO (SIOF)

Rev. 3.00 Jan. 18, 2008 Page 733 of 1458

REJ09B0033-0300

(8)

Synchronization-Pulse Output Mode at End of Each Slot (SYNCAT Bit = 1)

Synchronous pulse method, falling edge sampling, slot No.0 used for left-channel data, slot No.1

used for right-channel data, slot No.2 used for control channel 0 data, slot No.3 used for control

channel 1 data, and frame length = 128 bits

In this mode, valid data must be set to slot No. 0.

SIOFSCK

SIOFRxD

SIOFTxD

SIOFSYNC

TRMD[1:0]=00 or 10,

TDLE=1,

RDLE=1,

CD0E=1,

REDG=0,

TDLA[3:0]=0000,

RDLA[3:0]=0000,

CD0A[3:0]=0010,

FL[3:0]=1110 (frame length: 128 bits),

TDRE=1,

RDRE=1,

CD1E=1,

TDRA[3:0]=0001,

RDRA[3:0]=0001,

CD1A[3:0]=0011

L-channel

data

R-channel

data

Control

channel 0

Control

channel 1

Slot No.0

Slot No.1

Slot No.2

Slot No.3

Slot No.4

Slot No.5

Slot No.6

Slot No.7

Specifications:

1 frame

Figure 21.20

Transmit and Receive Timing (16-Bit Stereo Data)

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