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SH7721 Datasheet(PDF) 798 Page - Renesas Technology Corp |
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SH7721 Datasheet(HTML) 798 Page - Renesas Technology Corp |
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798 / 1524 page ![]() Section 22 Analog Front End Interface (AFEIF) Rev. 3.00 Jan. 18, 2008 Page 736 of 1458 REJ09B0033-0300 22.2 Input/Output Pins Table 22.1 shows the pins for AFE interface. Table 22.1 Pin Configuration Pin Name I/O Function AFE_RDET Input Ringing signal input AFE_RLYCNT Output On-hook control signal AFE_SCLK Input Shift clock AFE_FS Input Frame synchronization signal AFE_RXIN Input Serial receive data AFE_HC1 Output AFE hardware control signal AFE_TXOUT Output Serial transmit data 22.3 Register Configuration Registers for AFEIF are shown below. Byte access registers to these is inhibited. • AFEIF control register 1 (ACTR1) • AFEIF control register 2 (ACTR2) • AFEIF status register 1 (ASTR1) • AFEIF status register 2 (ASTR2) • Make ratio count register (MRCR) • Minimum pose count register (MPCR) • Dial number queue (DPNQ) • Ringing pulse counter (RCNT) • AFE control data register (ACDR) • AFE status data register (ASDR) • Transmit data FIFO port (TDFP) • Receive data FIFO port (RDFP) |
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