SH7721 datasheet(800/1524 Pages) RENESAS

Part #	SH7721

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	1524 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 22

Analog Front End Interface (AFEIF)

Rev. 3.00 Jan. 18, 2008 Page 738 of 1458

REJ09B0033-0300

Bit

Bit Name

Initial Value

R/W

Description

R/W

Transmit Enable

0: Transmit operation is disabled. The READ

pointer of FIFO is stacked to the first address.

WRITE pointer is reset when 0 is written to this

bit. TFEM and THEM bits in ASTR1 is set to 1

at that time.

1: Transmit operation is enabled.

R/W

Receive Enable

0: Receive operation is disabled. The READ

/WRITE pointer is fixed to the first address.

Bits RFFM and RHFM in ASTR1 are set to 1 at

that time.

1: Receive operation is enabled

Table 22.2

FIFO Interrupt Size

Description

Bit 4:

FFSZ2

Bit 3:

FFSZ1

Bit 2:

FFSZ0

FIFO Size

TFE/RFF

THE/RHF

128

128 empty/full

64 empty/full

(Initial value)

64 empty/full

32 empty/full

16 empty/full

8 empty/full

4 empty/full

2 empty/full

1 empty/full

96 empty/full

48 empty/full

SH7721 Datasheet(PDF) 800 Page - Renesas Technology Corp

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