SH7721 datasheet(802/1524 Pages) RENESAS

802 / 1524 page

Section 22

Analog Front End Interface (AFEIF)

Rev. 3.00 Jan. 18, 2008 Page 740 of 1458

REJ09B0033-0300

22.3.2

Make Ratio Count Register (MRCR)

MRCR is the counter that specifies make ratio of dial pulse. Make interval is specified with

AFE_FS as base clock of 9,600 Hz.

Pulse signal is not output when an invalid data (a data that is greater than 1E0H in case of PPS = 1

(20 pps), or a data that is greater than 3C0H in case of PPS = 0 (10 pps)) was input.

Bit

Bit Name

Initial Value

R/W

Description

15 to 10



All 0

Reserved

These bits are always read as 0. The write

value should always be 0.

9 to 0

MRCR9 to

MRCR0

R/W

Specifies make ratio of dial pulse.

22.3.3

Minimum Pause Count Register (MPCR)

MPCR is a counter that sets the dial number interval of the dial pulse. The interval is specified

with AFE_FS as base clock of 9600 Hz.

Bit

Bit Name

Initial Value

R/W

Description

15 to 0

MPCR15 to

MPCR0

R/W

Sets the dial number interval of the dial pulse.

22.3.4

AFEIF Status Register 1 and 2 (ASTR1, ASTR2)

ASTR is the control register for AFEIF, and composed of ASTR1 and ASTR2. ASTR1 is mainly

used for transmit/receive FIFO interrupt control commands. ASTR2 is used for DAA interrupt

control commands. See section 22.4.1, Interrupt Timing for more detail about interrupt handling.

(1)

AFEIF Status Register 1 (ASTR1)

ASTR1 is composed by interrupt status flags (4 bits) relating transmit/receive FIFO and mask

flags (4 bits) for transmit/receive FIFO interrupt signal. Status flag displays full/empty interrupt

status of transmit/receive FIFO and half size interrupt status for FIFO. FIFO empty (TFE) and

FIFO half size interrupt (THE) shows "1" as initial value, because transmit FIFO is empty after

power on reset. These interrupt flags are to be cleared with the data write / read action to FIFO

from CPU.

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