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SH7721 Datasheet(PDF) 806 Page - Renesas Technology Corp |
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SH7721 Datasheet(HTML) 806 Page - Renesas Technology Corp |
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806 / 1524 page ![]() Section 22 Analog Front End Interface (AFEIF) Rev. 3.00 Jan. 18, 2008 Page 744 of 1458 REJ09B0033-0300 Bit Bit Name Initial Value R/W Description 1 DPE 0 R/W Dial Pulse End 0: Normal state [Clearing conditions] • Reset • Interrupt status 1 is read and then 0 is written to this bit 1: Dial pulse end interrupt [Setting conditions] • Output of all of dial pulse sequences completed or end command 0H detected • Illegal end (unspecified dial number and DPST set when RLYC bit (ACTR2) is low level) 0 RDEF 0 R/W Ringing Detect 0: Normal state [Clearing conditions] • Reset • Interrupt status 1 is read and then 0 is written to this bit 1: Ringing waveform detect [Setting condition] • Ringing waveform is input to AFE_RDET pin (Latched at rising edge) |
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