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SH7721 Datasheet(PDF) 810 Page - Renesas Technology Corp |
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SH7721 Datasheet(HTML) 810 Page - Renesas Technology Corp |
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810 / 1524 page  Section 22 Analog Front End Interface (AFEIF) Rev. 3.00 Jan. 18, 2008 Page 748 of 1458 REJ09B0033-0300 22.4 Operation 22.4.1 Interrupt Timing AFE interface module generates 3 types of interrupt: FIFO data transfer, ringing detect, and dial pulse transmit end. The timing of each interruption is described below. (1) FIFO Interrupt Timing Figure 22.2 shows interrupt timing of data transfer FIFO. Transmit FIFO generates the TFE and THE interrupts after the last data is transfer red shift register. Receive FIFO generates the RFF and RHF interrupt after the last data or specified word is transferred from shift register to FIFO. AFE_FS Data 1 Data 2 Half-1 Half First First+1 Half-1 Half AFE_TXOUT TFE/TTE AFE_FS AFE_RXIN RFF/RTF Figure 22.2 FIFO Interrupt Timing |
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