SH7721 datasheet(813/1524 Pages) RENESAS

813 / 1524 page

Section 22

Analog Front End Interface (AFEIF)

Rev. 3.00 Jan. 18, 2008 Page 751 of 1458

REJ09B0033-0300

(2)

HC Control Sequence

AFEIF module supports hardware control STLC7550 that is an AFE manufactured by ST

microelectronics. Figure 22.6 shows the AFE control sequence.

Data word

Control word

Data word

Write 1 to HC bit of ACTR1

Write "1" to HC bit of ACTR1

FS for data

AFE mode change

HC1 goes to 0

HC1 goes to 1

FS for control word

DATA

Sampling period

1/2 sampling period

Mode change

(3)

(5)

(4)

(2)

(1)

AFE_FS

AFE_TXOUT

AFE_HC1

AFEIF

STLC7550

HC0: Kept to 1

1. If the CPU write "1" to the HC bit of ACTR1, the AEFIF drives AFE_HC1 to "H" right after

transmit next data.

2. AFE fetches the HC1's status of "H" at rising edgge of next AFE_FS.

3. AFE output the FS at the next 1/2 sampling period and then AFEIF transfers the control

word in synchronization with AFE_FS.

4. AFEIF keeps AFE_HC1 to "H" for 2nd AFE_FS and return to "L" after transmit the control

word.

5. AFE fetches the AFE_HC1's status of "L" and changes the mode of itself.

Figure 22.6

AFE Control Sequence

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