SH7721 datasheet(809/1524 Pages) RENESAS

809 / 1524 page

Section 22

Analog Front End Interface (AFEIF)

Rev. 3.00 Jan. 18, 2008 Page 747 of 1458

REJ09B0033-0300

22.3.9

Transmit Data FIFO Port (TDFP)

TDFP is the write only port for transmit FIFO. Transmit FIFO has 128 stages (maximum), and can

generate interrupt of the data empty as well as of the threshold size specified by FFSZ (ACTR1).

Directly after the reset and when TE (ACTR1) bit is 0, the pointer of FIFO is set to the first

address and data becomes empty. The interrupt will occur when the TE bit (ACTR1) is written to

1 at that state. In normal case, TE bit should be changed after writing data into transmit FIFO.

Bit

Bit Name

Initial Value

R/W

Description

15 to 0

TDFP15 to

TDFP0

All 0

Write only port for transmit FIFO.

22.3.10

Receive Data FIFO Port (RDFP)

RDFP is the read only register for receive FIFO. Receive FIFO has 128 stages (maximum), and

can generate interrupt of the data full as well as of the threshold size specified by FFSZ (ACTR1).

Directly after the reset and when RE bit (ACTR1) is 0, the pointer of FIFO is fixed at the first

address and data from RDFP becomes undetermined.

Bit

Bit Name

Initial Value

R/W

Description

15 to 0

RDFP15 to

RDFP0

Undefined

Read only register for receive FIFO.

SH7721 Datasheet(PDF) 809 Page - Renesas Technology Corp