SH7721 datasheet(805/1524 Pages) RENESAS

805 / 1524 page

Section 22

Analog Front End Interface (AFEIF)

Rev. 3.00 Jan. 18, 2008 Page 743 of 1458

REJ09B0033-0300

Bit

Bit Name

Initial Value

R/W

Description

RHF

Receive FIFO Half Size Full

0: Normal state

[Clearing conditions]

• Reset

• Number of data in FIFO becomes smaller

than the half of the size that is indicated by

FFSZ

• RE bit (ACTR1) is set to 0

1: Rx FIFO half size interrupt

[Setting condition]

• The half of specified size with FFSZ

(ACTR1) of receive data is accumulated into

FIFO

(2)

AFEIF Status Register 2 (ASTR2)

ASTR2 is the register that is composed of interrupt status flag (2 bits) relating DAA control and

mask flag (2 bits) of interrupt signals for DAA control. Status flags shows statuses of ringing

detect interrupt, end of dial pulse output interrupt. Interrupt flags are cleared by 0 write after read

action of this register. Each Interrupt signal can be masked by each interrupt masks.

Bit

Bit Name

Initial Value

R/W

Description

15 to 10



All 0

Reserved

These bits are always read as 0. The write

value should always be 0.

DPEM

R/W

Dial Pulse End Interrupt Mask

0: Interrupt enable

1: Interrupt mask

RDETM

R/W

Ringing Detect Mask

0: Ringing interrupt enable

1: Ringing interrupt mask

7 to 2



All 0

Reserved

These bits are always read as 0. The write

value should always be 0.

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