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SH7721 Datasheet(PDF) 804 Page - Renesas Technology Corp |
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SH7721 Datasheet(HTML) 804 Page - Renesas Technology Corp |
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804 / 1524 page  Section 22 Analog Front End Interface (AFEIF) Rev. 3.00 Jan. 18, 2008 Page 742 of 1458 REJ09B0033-0300 Bit Bit Name Initial Value R/W Description 2 RFF 0 R Receive FIFO Full Interrupt 0: Normal state [Clearing conditions] • Reset • Number of data in FIFO becomes smaller than the size that is indicated with FFSZ (ACTR1) • RE bit (ACTR1) is set to 0 1: Rx FIFO full interrupt [Setting condition] • Specified size with FFSZ (ACTR1) of receive data is accumulated into FIFO 1 THE 1 R Transmit FIFO Half Size Empty 0: Normal state [Clearing condition] • Number of valid data in FIFO becomes greater than the half of the size that is indicated by FFSZ 1: Tx FIFO Half Size Interrupt [Setting conditions] • Reset • Number of valid data in FIFO becomes smaller than the half of the size that is indicated with FFSZ • TE bit (ACTR1) is set to 0 (THEM bit is set to 1) |
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