SH7721 datasheet(797/1524 Pages) RENESAS

797 / 1524 page

Section 22

Analog Front End Interface (AFEIF)

Rev. 3.00 Jan. 18, 2008 Page 735 of 1458

REJ09B0033-0300

Section 22

Analog Front End Interface (AFEIF)

This LSI has an AFE interface that supports softwaremodem. This AFE interface can efficiently

execute the modem processing, because it includes 128 stages of FIFO for each of transmission

and reception. This AFE interface also includes the interface to data access arrangement (DAA)

such as dial pulse generator circuit and ringing detection. Therefore, it is possible to establish a

modem system with a minimum of hardware.

22.1

Features

• Serial interface with FIFO

• Clock synchronized serial interface

• Transmit/receive FIFO size is 16 bits (maximum) × 128 words

• Transmit/receive interrupt threshold size is programmable

• Dial pulse generator circuit is included

• Ringing detection (calling signal) function is included

Figure 22.1 shows a block diagram of AFEIF.

Bus I/F

Peripheral bus

Ringing

detector

Dial pulse

generator

Control

registers

Transmit FIFO

16 bits

× 128 words

AFE control word

AFE status word

HC control

P/S

S/P

AFE_RXIN

AFE_HC1

AFE_TXOUT

AFE_SCLK

AFE_FS

AFE_RLYCNT

AFE_RDET

Receive FIFO

16 bits

× 128 words

Figure 22.1

Block Diagram of AFE Interface

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