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SH7721 Datasheet(PDF) 796 Page - Renesas Technology Corp |
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SH7721 Datasheet(HTML) 796 Page - Renesas Technology Corp |
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796 / 1524 page  Section 21 Serial I/O with FIFO (SIOF) Rev. 3.00 Jan. 18, 2008 Page 734 of 1458 REJ09B0033-0300 21.5 Usage Notes 21.5.1 Regarding SYNC Signal High Width when Restarting Transmission in Master Mode 2 (1) Problem If SYNC signal output is enabled (FSE bit = 1), while output of the SYNC signal is disabled by clearing the SICTR.FSE bit in master mode 2 to 0, the High period of the SYNC signal may more quickly become 1 bit long with the rising edge of the SYNC signal in the head frame. However, this period will not be generated after the second frame. SYNC TXD 17 bit width 32 bit (Valid data) 32 bit (Valid data) 1 bit long 16 bit width 16 bit width 16 bit width Figure 21.21 Frame Length (32-Bit) (2) How to Avoid the Problem To avoid this problem, either counter-measure (a) or (b) is recommended. (a) When outputting data to the head frame, write dummy data to the transmission FIFO and write valid data after the second frame. The data of the head frame should be read and omitted at the receive side. (b) Use a configuration that does not occur malfunction, even if the period of the SYNC signal becomes 1 bit longer than that of the value set in the head frame. |
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