SH7721 datasheet(875/1524 Pages) RENESAS

875 / 1524 page

Section 25

USB Function Controller (USBF)

Rev. 3.00 Jan. 18, 2008 Page 813 of 1458

REJ09B0033-0300

Bit

Bit Name

Initial Value

R/W Description

SETI

R/W Set Interface Command Detection

[Setting condition]

When the valid Set Interface command is detected.

[Clearing conditions]

• When reset

• When 0 is written to by CPU

25.3.4

Interrupt Flag Register 3 (IFR3)

IFR1 is an interrupt flag register for EP4 TS, EP4 TF, EP5 TS, and EP5 TR. When each flag is set

to 1 and the interrupt is enabled in the corresponding bit of IER3, an interrupt request is generated

as specified by the corresponding bit in ISR3. Clearing is performed by writing 0 to the bit to be

cleared. Writing 1 is not valid and nothing is changed.

Bit

Bit Name

Initial Value

R/W Description

7 to 4



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

EP5 TR

R/W EP5 (Isochronous-in) Transmit Request

Flag indicating the FIFO state of EP5.

After the SOF packet is received, the FIFO buffer is

switched automatically. The FIFO buffer which has

transmitted data to the host in the previous frame

(before SOF reception) can be written to by the CPU.

This bit indicates the transmit state in the previous

frame.

[Setting condition]

The FIFO buffer to be transmitted is empty when an IN

token is issued from the host to EP5.

[Clearing conditions]

• When reset

• When 0 is written to by CPU

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