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SH7721 Datasheet(PDF) 876 Page - Renesas Technology Corp

Part # SH7721
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  1524 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7721 Datasheet(HTML) 876 Page - Renesas Technology Corp

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Section 25
USB Function Controller (USBF)
Rev. 3.00 Jan. 18, 2008 Page 814 of 1458
REJ09B0033-0300
Bit
Bit Name
Initial Value
R/W Description
2
EP5 TS
0
R/W EP5 (Isochronous-in) Normal Transmission
Flag indicating the FIFO state of EP5.
After the SOF packet is received, the FIFO buffer is
switched automatically. The FIFO buffer which has
transmitted data to the host in the previous frame
(before SOF reception) can be written to by the CPU.
This bit indicates the transmit state in the previous
frame.
[Setting condition]
When a transmission was carried out normally in the
previous frame.
[Clearing conditions]
• When reset
• When 0 is written to by CPU
1
EP4 TF
0
R/W EP4 (Isochronous-out) Abnormal Reception
Flag indicating the FIFO state of EP4. Indicates the
state of the FIFO buffer that was readable after the
data reception is completed and the next SOF packet
is received.
[Setting condition]
When the transfer data from the host is abnormally
received (packet error) by EP4.
[Clearing conditions]
• When reset
• When 0 is written to by CPU
0
EP4 TS
0
R/W EP4 (Isochronous-out) Normal Reception
Flag indicating the FIFO state of EP4. Indicates the
state of the FIFO buffer that was readable after the
data reception is completed and the next SOF packet
is received.
[Setting condition]
When the transfer data from the host is normally
received by EP4.
[Clearing conditions]
• When reset
• When 0 is written to by CPU



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