SH7721 datasheet(996/1524 Pages) RENESAS

996 / 1524 page

Section 27

A/D Converter

Rev. 3.00

Jan. 18, 2008

Page 934 of 1458

REJ09B0033-0300

Bit

Bit Name

Initial Value

R/W

Description

ADST

R/W

A/D Start

Starts or stops A/D conversion. The ADST bit

remains set to 1 during A/D conversion.

0: A/D conversion is stopped

1: Single mode: A/D conversion starts; ADST is

automatically cleared to 0 when conversion ends

on all selected channels

Multi mode: A/D conversion starts; when

conversion is completed cycling through the

selected channels, ADST is automatically cleared

to 0

Scan mode: A/D conversion starts and continues;

A/D conversion is continuously performed until

ADST is cleared to 0 by software, by a reset, or by

a transition to standby mode

DMASL

R/W

DMAC Select

Selects an interrupt due to the end of A/D conversion

or activation of the DMAC. Set the DMASL bit while

A/D conversion is not being made.

0: An interrupt by the end of A/D conversion is

selected

1: Activation of the DMAC by the end of A/D

conversion is selected

Always read as 0 when each register of A/D is read

through CPU.



Trigger Enable

Enables or disables A/D conversion by external

trigger input.

00: Disables A/D conversion by external trigger input

01: Reserved (setting prohibited)

10: Reserved (setting prohibited)

11: A/D conversion is started at the rising edge of A/D

conversion trigger pin (

ADTRG)



Reserved

These bits are always read as 0. The write value

should always be 0.

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